Sinolink Securities Co., Ltd. (SH: 600109) has released a research report indicating that, from an industry cadence perspective, three-stage power supplies will progress through "upgrades to mature solutions, adoption of modular architectures, and evolution toward package-level and chip-level power delivery." In the near term, multi-phase Buck converters paired with DrMOS remain the dominant baseline. Rising AI chip power levels will drive increases in per-unit phase counts, per-phase current handling capabilities, low-DCR inductor usage, high-reliability capacitors, and advanced PCB content, delivering strong earnings visibility. In the medium term, solutions such as TLVR, modular POL, and VPD are expected to accelerate adoption, improving transient response, reducing power delivery network (PDN) losses, and alleviating board-space constraints. Over the long term, IVR, package-level power delivery, and backside power delivery will integrate deeply with advanced packaging, Chiplet, and HBM technologies. Vendors with platform synergies and forward-looking technology reserves are positioned to secure long-term strategic value.
The sustained release of AI computing demand is driving AI data center (AIDC) power architectures toward 800VDC high-voltage DC distribution and increased power electronics adoption. The power delivery bottleneck is now migrating downward from the facility and rack levels to the board and chip levels. As the final voltage regulation stage directly serving GPUs and ASICs, three-stage power supplies determine chip power stability, transient response capability, and compute performance realization. They are entering a systematic upgrade cycle alongside the surge in AI chip power consumption.
Demand Drivers: Chip Power Surge Makes Low-Voltage, High-Current the Core Challenge
Nvidia's data center GPU thermal design power (TDP) has climbed from 400W for the A100 to 1400W for the B300, a more than 2.5x increase in five years. With liquid cooling adoption, per-rack GPU deployment density and power density have further increased. Given the constraint that core voltages remain in the 0.6V-1.8V low-voltage range, power increases ultimately translate into amplified final-stage current delivery. Kilo-ampere level currents combined with milli-ohm PDN impedance cause I2R losses to scale quadratically. Simultaneously, rapid load fluctuations in AI chips impose stricter requirements on output voltage stability. Three-stage power supplies now face quadruple constraints of high current, high transient demands, limited space, and high efficiency, making architecture upgrades an inevitable path.
Technology Trajectory: Moving from Discrete Multi-Phase Buck Toward Modular, Vertical Power Delivery, and Package-Level Integration
In the near term, multi-phase Buck with DrMOS remains the mainstream baseline for GPU, CPU, and ASIC core power delivery. As single-chip power heads toward kilowatt levels, the number of power phases, per-phase current capability, digital control precision, and the associated magnetic components, capacitors, and high-layer-count PCBs are all expected to scale upward. In the medium term, TLVR, modular POL, and VPD vertical power delivery are expected to accelerate market entry, respectively improving transient response, shortening customer design cycles, reducing PDN impedance, and freeing up space around the chip. Over the long term, IVR, package-level power delivery, and backside power delivery will work in tandem with advanced packaging, Chiplet, and HBM, pushing three-stage power delivery further into the package and chip itself.
Industry Chain Impact: Core Components See Volume and Price Growth, Competitive Barriers Shift to System-Level Capabilities
For DrMOS, high-power, high-current requirements are driving linear growth in DrMOS content, with product specifications evolving from 50A toward 80A/90A and above. The top four overseas vendors command roughly 85% combined market share, and tight supply is opening a window for domestic substitution. For inductors, higher frequency operation and miniaturization are driving upgrades in magnetic materials and processes, resulting in simultaneous volume and price increases. For capacitors, MLCC content per unit is roughly 13x higher than in general-purpose servers, and tight supply for high-end part numbers is pushing prices upward. Going forward, MLCCs and silicon capacitors are expected to serve in layered applications that complement each other. For PCBs, embedded inductors and capacitors, high-layer-count constructions, and 3D structures are becoming key upgrade directions for high-power-density three-stage power supplies.
Competitive Landscape: Overseas Leaders Dominate, Domestic Players Accelerate Catch-Up
At the chip level, MPS and Infineon lead the multi-phase controller and DrMOS market. At the module level, Delta Electronics, Flex, and Vicor have built differentiated competitive advantages in full-chain system solutions, vertical power delivery products, and fractional power architectures, respectively. In the passive components segment, Murata and Cyntec hold advantages in high-end MLCCs and chip inductors. Among domestic players, 杰华特 (Joint Power Semiconductor) is accelerating product adoption for multi-phase controllers and DrMOS, 深南电路 (Shennan Circuits) and 中富电路 (Zhongfu Circuit) have deep expertise in three-stage power PCBs and achieved volume shipments, while 铂科新材 (Boke New Material) and 龙磁科技 (Longmag) are benefiting from high-end chip inductor upgrades.
Risk Warnings
Capital expenditure falling short of expectations; chip power increases underperforming forecasts; shifts in technology roadmaps; and delays in customer qualification and order ramp-up.